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BPSK_Simulation_for_AWGN_Rayleigh_Channels
- BPSK SYSTEM SIMULATION We simulate the generation of random variables r0 and r1, which constitutes the input to detector.The detector output is compared with the binary transmitted sequence and an error counter is used to count the number of bit e
EDA
- EDA实验序列信号检测器和模可变计数器，工程文件和VHDL文件-EDA test sequence signal detector and variable-counter model, project files and VHDL files
adc3
- take a input vector which is no of users of b[kx1] and code vector which will be a matrix now s=[Nxk],where then give to matched filter,non-correlating detector, by randomised sequence.-take a input vector which is no of users of b[kx1] and
adc4
- with channel, take a input vector which is no of users of b[kx1] and then give to matched filter,non-correlating detector, and non-adaptive mmse,see the results by hadamard by randomised sequence.
xu_lie_jian_ce_qi
- 本设计通过Moore状态机设计一序列检测计。当输入的序列含有预置的11100101序列中的正确顺序时，进入下一个状态，直到到达st8状态，一个序列检测完毕。值得注意的是，当输入为111100101时，检测计仍能检测出里面的11100101序列，同时，当一个序列检测完毕时，下一个序列的高位可以只含有两个11即输入为1100101时，检测计一样能检测一个正确的序列。-The design by Moore state machine to design a sequence of the detec
mealy_machine
- mealy_machine该代码为序列脉冲检测器当输入信号110时电路输出为1否则为0-mealy_machine the code sequence when the input signal pulse detector circuit 110 output is 1 0 otherwise
EDA3add
- 序列信号发生器与检测器设计：用状态机设计实现串行序列检测器的设计，先设计（可用原理图输入法）序列信号发生器产生序列：0111010011011010；再设计检测器，若检测到串行序列11010则输出为“1”，否则输出为“0”，并对其进行仿真和硬件测试。-Sequence signal generator and detector design: The Design and Implementation of a serial sequence of state machine design of
XLXH
- 完成序列为0111010011011010的序列生成器 2．用状态机设计实现串行序列11010的检测器 3. 若检测到符合要求的序列，则输出显示位为“1”，否则为“0” 4. 可对检测到的次数计数 -Complete sequence is 0111010011011010 sequence generator 2. State machine design using serial sequence of 11 010 detector 3. If the sequence i
seqdet
- 经典编码风格的序列检测器，综合效率高，很有学习价值。-Coding sequence of the classic style of the detector, integrated, high efficiency, great learning value.
8_1
- 一个具有置位、复位、左移和右移功能的八位移位寄存器/“01011010”序列检测器。移位寄存器电路端口为：异步清零输入端口rst，输入时钟clk，置数判断输入端口load，移位类型判断输入端口m，数据输入端口data[7:0]，输出端口q[7:0]。序列检测器电路端口为：异步清零输入端口rst，输入时钟clk，串行数据输入端口d，输出标志端口s。(A eight bit shift register / 01011010 sequence detector with set, reset, le
序列检测器
- 本例子为一个序列检测器的程序，序列为：110010010000100101００，检测的序列为10010(This example is a sequence detector procedure, the sequence is: 11001001000010010100, the detection sequence is 10010)
DDSRF-PLL
- 本文论述了在控制的一个重要方面电网连接的电源转换器，即检测基波正序分量的电网电压不平衡和扭曲的条件下。明确地,提出了一种积极的基于一种新的序列检测器双同步坐标系的解耦锁相环（双dq–PLL），完全消除了检测误差传统的同步参考框架（SRF–锁相环PLL）。(This paper deals with an important aspect in the control of grid connected power converters, that is, detecting the fundam
用VHDL设计移位寄存器
- 实现序列检测，让你通过VHDL语言实现序列数字的发生(Sequence detector code)
kebenchengxu
- VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，同步计数器，序列检测器的设计，序列信号发生器，一般状态机等等。(The small program of some textbooks. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3
1
- VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，序列检测器的设计，一般状态机等等。(VHDL code, some textbooks for small programs. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3 prio
2
- VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字时钟，序列检测器的设计，一般状态机等等。(VHDL code, some textbooks for small programs. It includes 3 line -8 line decoder, 4 selector 1 selector, 6 elevator, 8 line -3 encoder, 8 l
lab5_0131_micro
- matlab sequence detector
110序列检测器
- 110的序列检测器，添加了使能端检查其正确性(The sequence detector of 110 adds the enable end to check its correctness.)
6bit序列检测器
- 1、用数码管显示被检测的连续数字序列，MSB在前； 2、当输入的数字序列连续六个值等于一组串行码（如00011101）时输出高电平并报警显示，同时用两位数码管显示出现的次数。 3、串行码的值可设定(6bit sequence detector)
并网逆变器中全软件锁相环的设计与实现
- 讲述并网逆变器中全软件锁相环的设计与实现，，即检测基波正序分量的电网电压不平衡和扭曲的条件下。明确地,提出了一种积极的基于一种新的序列检测器双同步坐标系的解耦锁相环（双dq–PLL），完全消除了检测误差传统的同步参考框架（SRF–锁相环PLL）(and implementation of all software phase-locked loop in grid connected inverter is described, that is, detecting the positive a